You will be responsible for developing a deeper understanding of standard bus protocols like (AHB/AHB5/AXI4/ACE/CHI-B, C, D, E etc.) and develop SW Softmodel / RTL IPs / accelerated VIPs using C/C++/ SystemVerilog/SystemC/ UVM, make them perfect for Simulation (Questa) and Emulation (Platform), helping customers to deploy and use them in their Verification Environment.
Education and Years of Experience Requirements: BE/ME/BTech/MTech in Elctronics/Electrical Engineering/Computer Engineering or related stream with 2+ years of relevant experience.
- Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
- Understanding of verification tools like Simulator, Synthesis etc.
- Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
- Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
- Excellent written and verbal interpersonal skills
- Self-motivated and great teammate
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Mid-level Professional
Job Type: Full-time