To understand and contribute to the verification solutions for High Level Synthesis (HLS). The role provides an opportunity to be a part of the next wave in designing and verifying SOCs as the EDA industry moves to higher levels of designing in C++/SystemC. And all this while being a part of a fun-loving team with flexible work culture.
- Understand the intricacies of the tool and be an expert user.
- Provide a user perspective to enhance the usability of the product.
- Validation of the product by writing test plans and developing test cases.
- Analyze customer issues, identify bottlenecks and provide workarounds.
- Innovate by exploring and prototyping new areas for expansion of verification portfolio.
- Contribute to the product and the infrastructure by developing scripts.
- Hands-on knowledge of C/C++
- Basics of either one of Verilog/System Verilog/VHDL/SystemC
- Knowledge of one of the scripting languages like Perl, Tcl, Python.
- Good problem solving and analytical skills.
- Experience with LINUX platforms.
- Team player
- Self-motivated and independent thinker.
- Hard working, sincere and committed to work
Good to have
- Exposure to Synthesis, Simulation and other verification methodologies.
- Good presentation and listening skills
Education: B.Tech or M.Tech in EE/ECE from a reputed engineering college.
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time