This position is open to new Graduates 2020 graduate who have a bachelor or masters degree in Electrical or Computer
Engineering. Course work and project experience with VLSI design, HDL Synthesis, VLSI testing and design for testability.
Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test
generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes scan based
testing, Memory BIST, LogicBIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies
desired. Preferred experience in specific areas: Operating Systems: UNIX, Linux, Sun Solaris. Languages: Verilog
(Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++. CAD Tools: Synthesis, Simulation, ATPG,
Memory BIST, Logic BIST, Boundary Scan. Familiarity with FastScan, FlexTest, LBIST Architect, MBIST Architect, and BSD
Architect a plus. Excellent verbal and written communication skills; self-motivated and results-oriented with strong problem
solving skills. Some Travel maybe required.
Organization: Digital Industries
Company: Mentor Graphics (Shanghai) Electronic Technology Co., Ltd.
Experience Level: Recent College Graduate
Job Type: Full-time