Verification Engineer_MTS-SISW-Mentor

Job Description

Position: Design and Verification Engineer

About group: Veloce Transactors  (Accelerated Verification IPs)  Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group is responsible for developing transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and expanding further.

Work Experience: 2 to 6 years

Education: (BE/BTech/ME/MTech/MS) from any of the premier engineering institutes.

Roles & Responsibilities:

Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesizable design using Verilog/System Verilog.

Primary Technical skills:

1.      Hands on experience on the protocol e.g. PCIe (preferable)/ USB/ Ethernet/ AMBA in Design or Verification.

2.      Good understanding of IP Verification Methodologies, Verification procedures and practices are plus

3.      Verilog / System Verilog / System C

4.      RTL in developed for FPGAs/ASICs/IPs

5.      He/ She must be able to create verification test plans and environments, testcase development, VIP usage, and the ability to debug of defects found through verification processes. 

6.      He/ She would need to engage with customers for Deployment and R&D assistance.

7.      Exposure of object oriented programming using languages such as C++ is advantage

8.      Experience in scripting languages such as Perl, Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc


Organization: Digital Industries

Company: Mentor Graphics (India) Private Limited

Experience Level: Experienced Professional

Job Type: Full-time

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