About the group: Questa Coverage R&D group.
It is a core R&D team working on simulation based code coverage of HDL designs. Charter of the team is to bring out state of the art coverage solution to improve over-all verification productivity.
A very energetic and enthusiastic team of motivated individuals.
Job-Duties: We are looking for a highly motivated software engineer to work in the Questa engineering team of the Mentor Graphics DVT Division.
· Development responsibilities will include core algorithmic advances and software design/architecture.
· You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to create new engines and support existent code.
· Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success.
· Good knowledge of C/C++, algorithm and data structures
· Experience with UNIX and / or LINUX platforms is necessary
· Good problem solving and analytical skills
· The person should be self-motivated and can work independently.
· Should be able to guide others, towards project completion.
Good to have
· Knowledge of Verilog, System Verilog, VHDL.
· Experience in parallel algorithms, job distribution.
· Exposure to Simulation or Formal based verification methodologies would be a plus
· Experienced in Coverage implementation (UCIS, Finite State Machines and other code and functional coverage metrics)
Education: B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college.
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time