R&D SW Engineer - Velsyn compile - SISW-MG

Job Description

During the current global health crisis, the priority for Siemens Digital Industries Software is the health and wellbeing of our entire community including current and future employees, which may add time to our hiring processes.  We appreciate your patience and invite you to visit our website to learn more about how Siemens is responding to the pandemic.  

Velsyn compile team is working on the core platform compile for hardware assisted function verification. This is a complex software dealing with varying concepts based on Graph Algorithms, Compiler optimizations, Logic Synthesis, Timing Analysis, Logic Partitioning etc.


As a member of the team, one will be working primarily on C++ and will be responsible for the design and development of various pieces of the overall compiler.

Job Qualification:

Should have - 

  • More than 3 years of experience in software development
  • Good knowledge of C++, algorithm and data structures
  • Good problem solving and analytical skills
  • The person should be self-motivated and can work independently.
  • Should be able to guide others, towards project completion.

Good to have

  • Knowledge of Verilog, System Verilog, VHDL.
  • Understanding of gate level digital logic design.
  • Experience in parallel algorithms, job distribution.
  • Knowledge of scripting languages (PERL, Python or Groovy) would be useful.
  • Experience in compiler/simulator development.

Job Qualifications:

  • B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college
  • Exp - 3-6 years


Organization: Digital Industries

Company: Mentor Graphics (India) Private Limited

Experience Level: Experienced Professional

Job Type: Full-time

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