Formal Verification Technologist - SISW - MG 208057

Job Description

During the current global health crisis, the priority for Siemens Digital Industries Software is the health and well being of our entire community including current and future employees, which may add time to our hiring processes.  We appreciate your patience and invite you to visit our website to learn more about how Siemens is responding to the pandemic.  




Company: SISW-MG
Job Title:   Formal Verification Technologist - 208057
Job Location: USA - CA - Fremont
Job Category: Applications Engineering


Job Description:

We are seeking a highly motivated individual who will be a senior member of the technology staff for the Calypto Systems Formal Verification solutions. 

The Formal Verification Technologist team plays a key role as technical experts supporting and driving new methodologies of verification in raising the design/verification abstraction to C and driving the rapid growth of the Catapult High-Level Synthesis products. 

The position works closely with both a dedicated FAE and Sales team and directly with customers to help solve problems, interface into R&D as a customer advocate and serve as world-wide technical expert. 

The ideal candidate is deeply technical with extensive experience in Formal verification and/or ASIC design, has strong communication skills,experience working with customers and is self-motivated and can work independently. 

Travel required.

Specific Responsibilities 
• Work with Catapult HLS customers (both experienced and new to HLS) to drive deployment of SLEC-HLS formal equivalence for C->RTL; working with them to both get their designs up and running successfully, understand their current verification methodology and efficiently compliment this with new formal methodology. 

• Work with R&D and product marketing to collaboratively drive user requirements gathered from your experience and customers and field engineers for SLEC C->RTL ease of use and scalability. 

• Create and deliver various example designs and reference flows for SLEC C->RTL(both HLS and Manual) and verification methodology documents using in-depth understanding of formal methods and IC design flows and tools. 

• Create and deliver coding style recommendations and guidelines to help ease adoption of SLEC-HLS formal verification for Catapult HLS users. 

• Create and deliver technical training for experienced AE’s and customers in addition to technical white papers, application notes and technical presentations • Lead agile teams with R&D for SLEC with a focus on requirements and deliverables



Job Qualifications:

• BS/MSEE or related field experience required

• Solid background in RTL design for ASIC/FPGA with 10+ years relevant work experience

• Solid background and experience with Formal verification tools and approaches; specifically logical equivalence and experience with C->RTL tools such as Jasper/Hector, etc preferred.

• Knowledge of C++ and/or SystemC and object-oriented design preferred

• Experience with HLS preferred

• Experience with ASIC RTL synthesis tools (Design Compiler, RTL Compiler, etc) preferred

• Demonstrated strength in problem solving skills

• Extremely strong communication skills and proven track-record of working collaboratively with both R&D technical team and other marketing and sales

•Strong presentation, verbal and written communication skills

Travel: Travel including some international travel will be required


This position may require access to export-controlled technology. If an export license is required and Mentor Graphics elects to apply for such a license, then candidates must be approved and licensed by the applicable government authorities as a condition of employment.


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Organization: Digital Industries

Company: Mentor Graphics Corporation

Experience Level: Experienced Professional

Job Type: Full-time



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