VTL Design and Verification Engineer

Position: Design and Verification Engineer

About group: Veloce Transactors  (Accelerated Verification IPs)  Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group is responsible for developing transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and expanding further.

Work Experience: 2 to 6 years

Education: (BE/BTech/ME/MTech/MS) from any of the premier engineering institutes.

Roles & Responsibilities:

Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesizable design using verilog/System Verilog.

Primary Technical skills:

Hands on experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification.
Good understanding of IP Verification Methodologies, Verification procedures and practices are plus
Verilog / System Verilog / System C
RTL in developed for FPGAs/ASICs/IPs
He/ She must be able to create verification test plans and environments, testcase development, VIP usage, and the ability to debug of defects found through verification processes. 
He/ She would need to engage with customers for Deployment and R&D assistance.
Exposure of object oriented programming using languages such as C++ is advantage
Experience in scripting languages such as Perl,
Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc

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