We are seeking a Corporate Application Engineer to provide technical support to our customers using our Tessent Design-For-Test products , and to provide product instruction to our customers and field personnel. This role will allow you to better understand DFT techniques and usage on design in many IC’s used in industries like AI, Automotive, Cellular Phone and many more.
Related responsibilities include: Some travel (less than 10%). : Keeping current on Scan Insertion, ATPG, BIST and Diagnosis tools; working with our Applications Engineers and Customers worldwide to solve technical DFT issues; developing and delivering best in class DFT product and flow support.dr
Education: BSEE/MSEE (Master’s degree preferred). At least three years of experience in IC/VLSI design and specifically IC/VLSI testing and design for testability. Experience with design, simulation, and verification of IC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This should include at least in part scan-based testing, Test Compression, Memory BIST, Logic BIST, and Boundary Scan (1149.1) as well as Diagnosis of test failures. Knowledge of scan data compression methodologies and ATPG flows and or MemoryBIST Flows is desired.
CAD Tool Experience a plus: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Strong troubleshooting skills and ability to break a complex problem into its components. Excellent interpersonal communication skills and customer facing skills are a must.
Preferred experience in specific areas: Operating Systems: UNIX, Linux. Languages: Verilog (Behavioral, RTL, gate level), System Verilog, VHDL (Behavioral, RTL, gate level), TCL
Organization: Digital Industries
Company: Mentor Graphics (Ireland) Ltd, Taiwan Branch
Experience Level: Early Professional
Job Type: Full-time