Working on 7nm and 5nm designs with various customers for deployment of Aprisa place and route tools.
Expertise in solving custorner's problems for critical designs to achieve desired performance, area and power targets.
Responsible to develop flow and methodology for doing placement, CTS and routing.
Provide training and technical support to customers using Aprisa tools
Typically requires minimum of 2-10 years of experience in Physical Design with mainstream P&R tools
Hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and/or Full Chip designs.
Hands-on experience with commercial place & route tools like Synopsys-lCC2, Cadence-lnnovus or Aprisa is a must.
Tapeout experience of 2 or more projects is a must.
Good understanding of timing, power and area trade-offs.
Ability to pickup new flows, learn on the job and influence QOR is a must.
Experience delivering designs with multiple voltage islands and top-level floorplanning & chip-assembly is a plus.
Strong verbal and written communication skills; good presentation skills
Good problem solving and debugging skills
BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering.
ME/M.Tech in VLSI or Microelectronics is a plus.
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time