Product Engineer – Functional Verification

Job Description

During the current global health crisis, the priority for Siemens Digital Industries Software is the health and well-being of our entire community including current and future employees, which may add time to our hiring processes.  We appreciate your patience and invite you to visit our website to learn more about how Siemens is responding to the pandemic. 

“At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow‘s reality. Find out more about the Digital world of Siemens here:"

Job Responsibilities
  • Contribute to the success of Siemens by increasing customer satisfaction and productivity with Siemens Scalable Verification products 
  • Develop and deliver technical training on new features and product updates 
  • Develop Technical content for Siemen’s knowledge base
  • Create new functional specification based on the customers’ technical requirements and work closely with R&D in getting it implemented. This will include an understanding and communication of the urgency and impact of these issues to the R&D.
  • Work with Field team in understanding customer needs on FV, involve and work with their projects for using the right methodologies and Siemens tools for successful project completion.
  • Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; drive competitive replacements, Provide support to customers during critical Project implementation phases.
  • Provide training and technical support to customers using Siemens tools
Job Qualifications
  • Required BE/B.Tech/M.Tech/M. s in Electronics and Communication (E&C) or Electrical or Telecom Engineering.
  • 3-10 years in the Functional Verification domain
  • Stronghold on VHDL/Verilog and SystemVerilog and UVM knowledge
  • Simulation/Verification using directed tests, constraint random testing, assertions, and coverage driven verification methods
  • RTL and Gate Level (GLS) verification and debug
  • Low power verification techniques using UPF and CPF
  • Working knowledge of AVM, OVM, VMM, UVM, and experience of using one of these methodologies in at least one complex project.
  • Protocol Knowledge would be added advantage.
  • Strong working knowledge in EDA tools like Questa, VCS, NCSim, IUS, Verdi tools

Organization: Digital Industries

Company: Siemens Electronic Design Automation (Korea) LLC

Experience Level: Experienced Professional

Job Type: Full-time

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