As a Senior Member Technical Staff in an R&D team, one will be working primarily on C++ and will be responsible for the design and development of various pieces of the RTL synthesis.
1-5 years of experience in software development
B.Tech/M.Tech in CSE/ECE/EE from a reputed engineering college
Good knowledge of C/C++, Data structure & Algorithms.
Good problem solving and analytical skills
Good to have
Understanding of RTL and gate level digital logic design.
Knowledge of Verilog, System Verilog, VHDL.
Knowledge of UPF and power synthesis.
Knowledge of scripting languages (Tcl, csh, Python) would be useful.
Experience in synthesis tool development.
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Mid-level Professional
Job Type: Full-time