At Siemens we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow’s reality. Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds
- BSEE or BSCS, or equivalent; MSEE preferred
- 5+ years of experience in a design engineering role focusing on functional verification
- 5+ years of ASIC/FPGA verification experience using SystemVerilog / UVM
- Must have experience in: Developing verification plans Designing and implementing SystemVerilog / UVM test benches for constrained-random verification Developing functional coverage models. Writing and debugging directed and random test cases Enabling test benches for hardware acceleration
- Experience with automation/scripting (Perl, sed, awk, tcl/tk, sh)
- C programming desirable. SystemC and C++ used in conjunction with chip design and verification highly desired
- Good communication skills
- RTL design experience and knowledge of standard protocols (such as PCIe) is a plus
- FPGA experience is a plus
- Deliver consulting services covering a broad range of functional verification and emulation activities.
- Responsible for leading and executing consulting programs and working with customers to implement and deploy advanced verification methodologies.
- Help customers leverage the full capability of Mentor verification tools and technologies.
- Communicate customer technical requirements to product marketing
- Travel will be involved mainly within the U.S.
Where permitted by applicable law, Siemens may require employees to be fully vaccinated against COVID-19 based on job requirements, and in accordance with an accommodation based on legally protected reasons
Organization: Digital Industries
Company: Siemens Industry Software Inc.
Experience Level: Experienced Professional
Job Type: Full-time
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