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Sr. Corporate Application Engineer – Design and Verification Tools

Job Description

During the current global health crisis, the priority for Siemens Digital Industries Software is the health and well-being of our entire community including current and future employees, which may add time to our hiring processes.  We appreciate your patience and invite you to visit our website to learn more about how Siemens is responding to the pandemic. 

“At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow‘s reality. Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds

The Corporate Applications Engineer is a dynamic, exciting position where you can utilize your physical verification and design skills to enable the success of our customers and our business. You will assist customers by deploying Siemens EDA’s physical verification software, aiding them to solve complex verification and design challenges.

Job Responsibilities
  • Troubleshoot technical obstacles to productivity with Siemens EDA’s software
  • Track and update customer issues using Siemens EDA’s processes and tracking tools
  • Develop and deliver technical training on new features and product updates
  • Develop technical content for Siemens EDA’s knowledge base
  • Communicate customers’ technical requirements as well as priority and impact, influence the product team to meet customers' needs and shape product direction
  • Develop positive, technical relationships with our customers, sales teams, and product engineering teams.
  • Work collaboratively with the customer & sales teams to ensure the mutual success of the engagement.
  • Perform early access testing and collaborate with R&D to improve product quality and capabilities.
  • Some travel is required for support and training purposes
Job Qualifications
  • BSEE or MSEE-related engineering discipline plus 5+ years of experience in the EDA, or Semiconductor field
  • Experience in constrained-random testing, assertions (PSL or SV), static formal verification methods, clock domain crossing verification, LINT, and formal design checking methods is also desirable
  • Requires well-developed verbal and written communication skills in English
  • Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams
  • Good Knowledge of C/C++
  • Familiarity with Siemens EDA’s tools such as Questa or other similar RTL Verification tools
  • Good knowledge of UVM and other such verification methodologies
  • Good working knowledge in the areas of VHDL /Verilog and SystemVerilog for ASIC or FPGA design and verification is mandatory
  • Significant experience in implementing ASIC or FPGA hardware design and verification (simulation) using RTL flows

Organization: Digital Industries

Company: Siemens Electronic Design Automation (Korea) LLC

Experience Level: Experienced Professional

Job Type: Full-time

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