Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

Key Responsibilities:

As a Functional Verification Application Support Engineer, you are the first point of contact for our customers when they have any product usage questions or experience any product issues. You will use your technical expertise to understand the customer’s problem and to help solve it. Working directly with our customers, you will support them on how to best use our tools to do what they require. When problems occur, you will look for a possible workaround and explain the problem to our internal R&D and work with them to provide the customer with a fix. As a Functional Verification Application Support Engineer, you also collaborate with our Field Application Engineers in evaluations and demonstrations of our tools at customer sites and act as a point of contact for customer needs by making enhancement requests so that the tools best meet customer needs!

1. Solving technical obstacles to the customer’s productivity with Siemens EDA’ software.
2. Tracking and updating customer issues using Siemens EDA’ processes and tracking tools.
3. Developing and delivering technical training on new features and product updates
4. Developing technical content for Siemens EDA’ knowledgebase.
5. Communicating customers’ technical requirements as well as priority and impact, influencing the product team to meet customer's needs and shape product direction.
6. Developing positive, technical relationships with our customers, sales teams, and the product engineering teams.
7. Work collaboratively with the customer & sales teams to ensure mutual success of any engagement.
8. Perform early access testing and collaborate with R&D to improve product quality and capabilities.

Qualifications:

1. Knowledge of Verification Planning and Management methods (UVM or OVM)
2. Significant experience of implementing ASIC or FPGA hardware design and verification (simulation) using RTL flows.
3. Proven understanding in the areas VHDL / Verilog and System Verilog for ASIC or FPGA design and verification is required.
4. Familiarity with Siemens EDA tools such as Questa or other similar RTL Verification tools.
5. Experience in constrained-random testing, assertions (PSL or SV), static formal verification methods, clock domain crossing verification, LINT and formal design checking methods is also desirable.
6. Knowledge of C/C++
7. Master's or bachelor’s Engineering degree or a Technical Diploma in Electronic Engineering plus 3+ years of experience in the EDA, or semiconductor industry

We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.

Qualified Applicants must be legally authorized for employment in the United States. Qualified Applicants will not require employer sponsored work authorization now or in the future for employment in the United States.

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