Employer: Siemens Industry Software Inc.

Job Title: Product Engineer [MULTIPLE POSITIONS]

Job Location: Wilsonville, OR

Job Type: Full Time

Rate of Pay: The salary range for this position in Wilsonville, OR is $127,878.00 - $157,700.00 per year and this role may be eligible to earn incentive compensation. Siemens offers a variety of health and wellness benefits to employees. Details regarding our benefits can be found here: www.benefitsquickstart.com. In addition, this position is eligible for time off in accordance with Company policies, including paid sick leave, paid parental leave, PTO (for non-exempt employees) or non-accrued flexible vacation (for exempt employees).

Duties: Work collaboratively with Tessent R&D to prototype, evaluate, and test new DFT products and features within complex IC design flows. Work with customers as well as business stakeholders such as regional application engineers, global support engineers, and marketing. Lead beta programs and support beta partners. Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes. Develop and review tool documentation such as User and Reference manuals. Develop new flows to integrate and test new Tessent technologies. Create test cases with Tessent and some 3rd party tools to replicate customer issues. Explain complex principles in simple terms to broad audiences. Review customer and AE questions, discussing steps to resolution internally. Propose support responses, with feedback from senior engineers. Attend internal meetings to learn the process for PE role.

Requirements: Employer will accept a Bachelor’s degree, or foreign equivalent, in Electrical Engineering, Computer Engineering or related field and 24 months of experience in the job offered or in a Product Engineer-related occupation. Alternatively, employer will accept a Master's degree, or foreign equivalent, in Electrical Engineering, Computer Engineering or related field and no experience.

Position requires coursework, internship in DFT (Design for Test), or experience in the following:

1. Experience in DFT for ASICs and SOCs including Automatic test pattern generation (ATPG), Internal scan & embedded scan compression (EDT), and Memory built-in self-test (MBIST) and repair (BISR).

2. Experience with Advanced DFT implementation technologies including Packetized test delivery (SSN), On-chip Clock Control (OCC), and hierarchical DFT implementation.

3. Experience with chip front-end design disciplines including RTL coding and verification using Verilog/SystemVerilog and Simulation.

4. Experience with chip back-end design disciplines Synthesis, Static Timing Analysis, Simulation and debugging Scan, ATPG, and DRCs, and ATPG Coverage analysis and improvement.

5. Creating design flows and testcases to replicate behaviors or to setup new features.

6. Experience with Tessent products including Tessent Streaming Scan Network, Tessent TestKompress, Tessent ScanPro, Tessent IJTAG, Tessent MemoryBIST, and Tessent Shell.

[on-site role]

Referral Program: Incentives offered through the Company’s Employee Referral Program are applicable to this position.

CONTACT : Apply within this posting.

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