**This is a US-Based opportunity.**

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

Do you like a challenge, are you a complex thinker who likes to solve problems? If so, then you might be the new team member we are searching for. At Siemens, your curiosity matters. As part of the Siemens family, we pride ourselves on a business culture that enables open, creative thinking, and we deeply value our employees and their contributions towards our clients' success, as well as our own.

Qualified Applicants must be legally authorized for employment in the United States. Qualified Applicants will not require employer sponsored work authorization now or in the future for employment in the United States.

Job Summary

As a member of the HPCWorks Product Management team at Siemens, you will take the lead in shaping the future of Siemens VOV products, including Altair Accelerator, Accelerator+, and Flowtracer, - industry-leading workload management solutions purpose-built for semiconductor design and verification workflows. This is a strategic and technical role where you'll define the roadmap, drive innovation, and ensure that our HPCWorks EDA tools continue to meet the evolving needs of chip design teams worldwide. You'll work at the intersection of customer insight, engineering excellence, and market strategy—collaborating with diverse teams across Siemens Digital Industries Software and the broader Siemens ecosystem to deliver impactful solutions that accelerate ECAD workflows, from RTL verification through physical design and Place & Route. If you're passionate about enabling the next generation of chip design through intelligent workload orchestration and workflow optimization, this is your opportunity to make a difference within one of the world's leading technology companies.

Key Responsibilities

• Own the Product Lifecycle: Define and execute the product strategy and roadmap for Siemens Altair VOV products, including Accelerator and Flowtracer, ensuring alignment with semiconductor industry trends, Siemens Digital Industries Software strategy, and the evolving needs of ECAD design and verification teams.
• Gather Insights: Engage with chip design teams, EDA partners, Siemens customers, and internal stakeholders to collect feedback on verification flows, P&R workflows, and regression management—prioritizing features that accelerate design closure and improve resource utilization.
• Collaborate Cross-Functionally: Work with engineering, QA, UX, documentation, sales and marketing teams across Siemens to deliver high-quality releases that meet the demanding requirements of semiconductor design environments. Leverage synergies with other Siemens EDA and PLM solutions.
• Drive Innovation: Lead initiatives to expand Accelerator and Flowtracer capabilities into emerging areas such as AI-driven job scheduling, cloud bursting for EDA workloads, containerized verification flows, advanced dependency management, and integration with modern DevOps practices for chip design.
• Market Intelligence: Monitor market trends in semiconductor design methodologies, competing job schedulers, and open-source communities to ensure Siemens maintains a leadership position.
• Communicate Value: Translate technical features into business value for semiconductor companies—demonstrating how Accelerator and Flowtracer reduce verification runtime, improve cluster utilization, and accelerate time-to-tapeout. Support go-to-market efforts including positioning, messaging, sales enablement, and product launches across Siemens' global sales organization.
• Represent the Product: Act as a subject matter expert at industry conferences (DAC, etc.), webinars, and customer design reviews, representing Siemens' comprehensive EDA and workload management solutions.

Qualifications

• Bachelor or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 4–7 years of experience in product management, technical marketing, or CAD/EDA engineering roles within the semiconductor industry.
• Hands-on experience with chip verification workflows including simulation, regression management, coverage analysis, and debug methodologies using industry-standard tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa).
• Working knowledge of Place & Route (P&R) workflows and physical design processes, including familiarity with tools such as Synopsys ICC/Fusion Compiler, Cadence Innovus, or similar.
• Understanding of ECAD infrastructure: Experience designing, configuring, or managing compute clusters and distributed computing environments for chip design workflows.
• Strong understanding of workload management concepts including job scheduling, dependency tracking, resource allocation, and distributed computing in design environments.
• Proven ability to work with engineering teams using Agile/Scrum methodologies.
• Excellent communication, analytical, and organizational skills with the ability to translate technical requirements into product features.
• A customer-first mindset and a track record of delivering user-focused products in demanding technical environments.

Preferred Experience

• Direct experience with Siemens Altair Accelerator and/or Flowtracer (or competitive  workload managers such as IBM Spectrum LSF or Grid Engine).
• Expertise in verification flows: Functional verification, formal verification, emulation/prototyping workflows, and regression management strategies.
• Experience with ECAD design methodologies across the full chip design flow from RTL to GDSII.
• Familiarity with Siemens EDA tools including Questa, Calibre, or other Siemens Digital Industries Software solutions.
• Knowledge of hybrid on-premise/cloud environments for EDA workloads and experience with cloud bursting strategies for compute-intensive design tasks.
• Familiarity with containerized EDA workflows and orchestration tools (e.g., Kubernetes, Docker, Singularity) in semiconductor design contexts.
• Understanding of AI/ML applications in chip design including ML-driven optimization, design space exploration, and intelligent job scheduling.
• Experience with HPC and distributed computing architectures supporting large-scale design teams.
• Prior involvement in EDA user communities, industry standards bodies, or enterprise software development.
• Background in DevOps practices for chip design including CI/CD for hardware verification and design automation.