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Technology Enablement Engineer(Tessent)

ID de l'offre
504168
Publié depuis
27-Avr-2026
Organisation
Industries numériques
Domaine d'activité
Recherche et développement
Entreprise
Siemens Electronic Design Automation (Korea) LLC
Niveau d'expérience
Expérimenté
Type de poste
Temps plein
Modalités de travail
Au bureau / sur site uniquement
Type de contrat
Contrat à durée indéterminée (CDI)
Lieu
  • Seongnam - Gyeonggi-do - Corée (République de)
We are looking for an experienced DFT (Design for Test) engineer. As a Technical Enablement Engineer, they will collaborate with application engineers, senior customers, and managers to develop or enhance complex computer-aided engineering design or manufacturing processes, while independently identifying customer needs and providing guidance on their DFT environments and architectures.

The job requires a broad understanding and strong knowledge of SoC DFT methodologies, including Scan, ATPG, and MBIST, as well as an understanding of DFT infrastructure such as Silicon Diagnosis.

The role is responsible for producing in-depth technical papers and delivering technical presentations to customers. Candidates must be able to work without supervision on complex projects and exercise independent judgment and discretion.

Drive product adoption.
Build and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes.
Work with customers as well as stakeholders such as regional application engineers, global support engineers, and marketing.
Work through complex technical issues and independently create solutions and new methodologies.
Explain complex principles in simple terms to broad audiences.
Strong English speaking and writing skills are required
Some travel, domestic and international.


Job Qualifications

- Education : BSEE/MSEE (Master’s degree preferred)

- Approximately 10 years of experience in the Design for Test is preferred.

- Familiar with VLSI design, VLSI testing and design testability.

- Experience with design, simulation, and verification of ASIC/VLSI circuits and systems, design verification and product test

generation preferred.

- In-depth understanding of Design for Test (DFT) structures is required.

- This includes scan-based testing, Memory BIST, Logic BIST, and Boundary Scan

- Knowledge of scan data compression methodologies and ATPG flows is desired.

- Preferred experience in specific areas :

* Operating Systems : UNIX, Linux

* Languages : Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), TCL, Perl, C/C++

* CAD Tools : Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan.

- Strong troubleshooting skills and ability to break a complex problem into its components

- Excellent interpersonal communication skills and customer facing skills are a must.



We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.



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